The Transformation Path of a Niche Foundry: How Powerchip (PSC) Seeks New Growth in 3D AI and Advanced Packaging

Event Overview

In June 2026, Powerchip Semiconductor Manufacturing (stock code 6770) released a company presentation disclosing the results of its strategic transformation: 2025 revenue reached NT$47 billion (approximately US$1.45 billion), a year-on-year increase of 4.5%; in Q1 2026 revenue, 3D AI business accounted for 3.2%, logic 52.8%, and memory 44%. The company operates 5 fabs (2 8-inch, 3 12-inch), with an estimated 1.63 million wafer shipments in 2025 and over 8,200 employees.

Behind these figures lies Powerchip's critical leap from a traditional DRAM foundry to diversified logic and memory foundry, and further to a 3D AI and advanced packaging platform. This article will analyze the significance of Powerchip's transformation for the global semiconductor industry from four dimensions: industry chain, technology roadmap, market competition, and regional layout.

Background: Evolution from DRAM Foundry to Niche Leader

• Powerchip Semiconductor was formerly a DRAM manufacturer and later transformed into a pure-play foundry. Its foundry model focuses on niche markets with non-leading process nodes:
• Memory foundry (≤1Gb DRAM) global share of 71%
• Pseudo SRAM share of 74%
• Touch Display Driver IC (TDDI) share of 55%

Although these markets are not large in scale, they have extremely high barriers—customers are mostly IDMs or Fabless companies in specific application areas, with strict requirements for mature process stability, low power consumption, and customization. Powerchip has more than 200 foundry platforms, supporting nodes from 350nm to 1Xnm, while providing aluminum and copper process options, and differentiated technologies such as 3D Interchip WoW (Wafer-on-Wafer) stacking.

In terms of ESG, Powerchip ranked 5th globally in the S&P Global 2024 Semiconductor Sustainability Yearbook, providing brand and compliance foundations for transformation.

In-Depth Analysis

Technology Impact: 3D WoW and Advanced Packaging Technology BarriersPSMC's core technology differentiation lies in 3D Interchip WoW stacking. Unlike TSMC's CoWoS or Intel's Foveros, PSMC's WoW uses wafer-to-wafer direct bonding without an interposer, making it suitable for heterogeneous integration of memory and logic chips. - Technology Route: Currently, PSMC's 3D AI business mainly targets scenarios such as edge AI inference and near-memory computing in data centers. Its 1Xnm logic process combined with WoW packaging enables high-bandwidth, low-latency chiplet interconnects. - Barriers: Bonding alignment precision, thermal management, and yield control for WoW stacking are the main challenges. PSMC leverages its long-term wafer-level process experience accumulated from DRAM manufacturing to gain advantages in defect density control. - Evolution Path: The company is developing a 2Xnm logic process and more advanced 3D integration capabilities, aiming to increase the 3D AI revenue share to over 10% (by 2027).

Supply Chain Impact: Which links in the industry chain benefit?

• PSMC's transformation directly affects the following links:
• Upstream Equipment & Materials: Increased demand for wafer bonding equipment (e.g., EV Group, SUSS MicroTec), specialty gases (for bonding interface cleaning), and high-purity silicon wafers. PSMC's 8-inch and 12-inch capacity expansion benefits wafer suppliers such as Shin-Etsu Chemical and SUMCO.
• Midstream Foundry: PSMC positions itself to compete differently from TSMC and UMC. TSMC focuses on advanced nodes (3nm/5nm) and high-end packaging (CoWoS), UMC concentrates on mature processes, while PSMC has exclusivity in memory foundry and 3D WoW.
• Downstream Packaging & Testing: PSMC's WoW technology can partially replace traditional packaging, but the back end still requires testing and final packaging services from ASE, Amkor, etc. The increase in 3D AI chips will drive demand for test equipment from Advantest and Teradyne.

Risk: If PSMC cannot rapidly improve the yield of its 3D technology, it may lose customers to TSMC's 3D Fabric platform or Intel's EMIB solution.

Competitive Landscape: How will the competitive landscape change?Powerchip's competitors can be divided into three groups: 1. Memory foundry field: Winbond and Macronix have advantages in NOR Flash and NAND Flash, but Powerchip's monopoly position in ≤1Gb DRAM is difficult to shake. 2. Mature logic foundry: UMC, SMIC, and Tower Semiconductor cover similar nodes, but Powerchip maintains its share through customer stickiness in memory and driver ICs. 3. Advanced packaging and 3D integration: TSMC (CoWoS, InFO, TSMC-SoIC), Intel (Foveros, EMIB), and Samsung (X-Cube) are the main competitors. Powerchip's WoW has advantages in cost and flexibility, especially suitable for small-to-medium batch, customized products, but its niche is narrow.

Market share estimate: Powerchip accounts for only about 1% of the global foundry market (by revenue), but holds a very high share in niche segments. With the growth of 3D AI revenue, its share in the advanced packaging market is expected to increase from the current <1% to 2-3% by 2028.

Regional Implications: Strengthening of Taiwan's supply chain and geopolitical risks

• Taiwan: All of Powerchip's factories are located in Taiwan (Hsinchu, Zhunan). Its transformation strengthens Taiwan's diversity in mature process and advanced packaging. However, over-concentration also faces geopolitical risks—if the Taiwan Strait situation becomes tense, Powerchip could become a pawn in the US-China game.
• Mainland China: Mainland China is rapidly catching up in memory foundry (e.g., Changxin Memory Technologies) and mature process (SMIC), so Powerchip's niche advantage may be eroded. However, 3D AI technology involves advanced packaging, and US export controls limit China's ability to obtain WoW equipment (EV Group's wafer bonders), giving Powerchip a first-mover advantage in the short term.
• United States and Japan: The US encourages domestic advanced packaging R&D through the CHIPS Act, but if Powerchip's WoW technology can collaborate with US AI chip design companies (such as AMD, Broadcom), it can enter the US supply chain. Japan's advantages in materials and equipment (such as Tokyo Electron) have synergies with Powerchip's process development.

Investment Perspective: Where is the long-term value?The capital market is focusing on Powerchip’s transformation flexibility: - Revenue structure optimization: 3D AI gross margin is higher than traditional logic and memory businesses (refer to the company’s presentation for gross margin turning positive in 2025). As its share increases, overall profitability will improve. - Asset sale value: Powerchip recently sold some assets (refer to the sharp rise in net profit in Q1 2026 from asset sales), indicating flexible cash flow management. - Valuation logic: If the 3D AI business matures, Powerchip’s comparable companies will shift from foundries to advanced packaging service providers, and valuation multiples (e.g., price-to-sales ratio) are expected to rise. Currently, PSC’s P/S is about 2.5x, while TSMC’s is about 8x, leaving room for a discount.

Long-Term Outlook: Possible Changes in 3-5 Years

• 3 years (2026-2028): Powerchip’s 3D AI revenue share may reach 10-15%, and it will enter the HBM base die foundry market. 2Xnm process mass production, WoW yield improved to over 90%.
• 5 years (2029-2030): If technology continues to break through, Powerchip may become the main foundry and packaging partner for edge AI chips. However, caution is needed regarding TSMC’s 3D Fabric platform squeezing small and medium customers.
• 10-year horizon: Powerchip needs to prove that it can independently support next-generation processes (e.g., below 1Xnm), otherwise it may become a single-technology platform company with an increased risk of acquisition.

Industry Chain Analysis: Impact on the Full Industry Chain

• Upstream: Powerchip’s demand for wafer bonding equipment, bonding materials (e.g., Cu-Cu bonding media), and inspection equipment will drive related markets. In terms of lithography machines, ASML’s DUV (immersion) remains the mainstay, with no need for EUV.
• Midstream: In logic foundry, Powerchip competes with UMC and SMIC at the 0.13μm-28nm nodes; in memory foundry, it competes with Winbond and Macronix. In 3D AI, it differentiates from TSMC, Samsung, and Intel in advanced packaging.
• Downstream: Powerchip’s customers include chip design companies in automotive electronics, IoT, display drivers, AI accelerators, and other fields. Its open foundry model and joint development program (JDP) enhance customer stickiness. However, there is downstream customer concentration risk: if the top five customers account for more than 50% of revenue (not disclosed), caution is warranted.

Conclusion## Conclusion

Powerchip's transformation is a typical case of mature foundries seeking differentiated value outside the advanced process race. Its core judgment:

1. Niche foundry moat is stable in the short term: In the ≤1Gb DRAM and pseudo-SRAM markets, Powerchip's market share and process experience are difficult to replace within 3-5 years. 2. 3D AI business is a second growth curve, but limited in scale: WoW technology is suitable for specific scenarios and cannot directly compete with TSMC's CoWoS; it needs to focus on small and medium customers and edge computing. 3. Geopolitical risks and opportunities coexist: The concentrated layout in Taiwan brings operational efficiency, but also increases supply chain resilience risks. Under the US-China technology decoupling, Powerchip can undertake some "China+1" orders, but needs to carefully balance.

For investors and industry observers, Powerchip provides a window to observe how "non-leading foundries" achieve sustainable growth through technological micro-innovation and niche strategies. Whether it can commercialize its 3D AI business and bring stable profits in the next three years will be a key verification point.